{"id":1430,"date":"2026-05-08T22:39:06","date_gmt":"2026-05-08T14:39:06","guid":{"rendered":"http:\/\/www.hanhhsir.cn\/?p=1430"},"modified":"2026-05-08T22:39:59","modified_gmt":"2026-05-08T14:39:59","slug":"%e5%9f%ba%e4%ba%8eahb%e7%9a%84%e5%9b%9b%e9%80%9a%e9%81%93dma%e6%8e%a7%e5%88%b6%e5%99%a8%e8%ae%be%e8%ae%a1-test_dma-v","status":"publish","type":"post","link":"http:\/\/www.hanhhsir.cn\/index.php\/2026\/05\/08\/%e5%9f%ba%e4%ba%8eahb%e7%9a%84%e5%9b%9b%e9%80%9a%e9%81%93dma%e6%8e%a7%e5%88%b6%e5%99%a8%e8%ae%be%e8%ae%a1-test_dma-v\/","title":{"rendered":"\u57fa\u4e8eAHB\u7684\u56db\u901a\u9053DMA\u63a7\u5236\u5668\u8bbe\u8ba1-test_dma.v"},"content":{"rendered":"

test_dma.v = DMA \u63a7\u5236\u5668\u7684\u4eff\u771f\u6d4b\u8bd5\u5e73\u53f0<\/strong>
\n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2022 \u4f8b\u5316\u4f60\u524d\u9762\u7684 dmac \u9876\u5c42<\/strong>
\n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2022 \u7528 sim_ahb_task \u6a21\u62df CPU \u914d\u7f6e DMA<\/strong>
\n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2022 \u6a21\u62df \u5916\u8bbe\u89e6\u53d1 DMA \u8bf7\u6c42<\/strong>
\n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2022 \u81ea\u52a8\u8dd1\u6d4b\u8bd5\u7528\u4f8b\uff0c\u770b DMA \u642c\u6570\u636e\u5bf9\u4e0d\u5bf9<\/strong><\/p>\n

`timescale 1ns\/10ps<\/p>\n

\/\/ ==============================<\/strong>
\n\/\/ \u6a21\u5757\uff1aDMA \u4eff\u771f\u6d4b\u8bd5\u9876\u5c42<\/strong>
\n\/\/ \u4f5c\u7528\uff1a\u7ed9DMA\u4f9b\u7535\u3001\u6a21\u62dfCPU\u3001\u6a21\u62df\u5916\u8bbe\u3001\u8dd1\u6d4b\u8bd5\u7528\u4f8b<\/strong>
\n\/\/ ==============================<\/strong>
\nmodule test_dma;<\/p>\n

\/\/ \u65f6\u949f\u5468\u671f\uff1a100ns \u2192 10MHz
\nparameter PERIOD = 100;<\/p>\n

\/\/ DMA \u5bc4\u5b58\u5668\u57fa\u5730\u5740\uff08\u548c dmac_intf \u4e00\u81f4\uff09
\nparameter BASE_ADDR= 32’h4000_0000;<\/p>\n

\/\/ \u901a\u9053\u4f7f\u80fd
\nparameter CH0_EN = 1;
\nparameter CH1_EN = 1;
\nparameter CH2_EN = 1;
\nparameter CH3_EN = 1;<\/p>\n

\/\/ \u901a\u9053\u65b9\u5411\u914d\u7f6e
\nparameter CH0_TGT = 32’h10;
\nparameter CH1_TGT = 32’h10;
\nparameter CH2_TGT = 32’h10;
\nparameter CH3_TGT = 32’h10;<\/p>\n

\/\/ ==============================
\n\/\/ DMA \u5bc4\u5b58\u5668\u5730\u5740\u6620\u5c04\uff08\u548c dmac_intf \u5b8c\u5168\u5bf9\u5e94\uff09
\n\/\/ ==============================
\nparameter CH0_CTRL = BASE_ADDR + 32’h0; \/\/ \u901a\u90530\u63a7\u5236
\nparameter CH1_CTRL = BASE_ADDR + 32’h12;
\nparameter CH2_CTRL = BASE_ADDR + 32’h24;
\nparameter CH3_CTRL = BASE_ADDR + 32’h36;<\/p>\n

parameter CH0_SOUR = BASE_ADDR + 32’h4; \/\/ \u901a\u90530\u6e90\u5730\u5740
\nparameter CH1_SOUR = BASE_ADDR + 32’h16;
\nparameter CH2_SOUR = BASE_ADDR + 32’h28;
\nparameter CH3_SOUR = BASE_ADDR + 32’h40;<\/p>\n

parameter CH0_DEST = BASE_ADDR + 32’h8; \/\/ \u901a\u90530\u76ee\u6807\u5730\u5740
\nparameter CH1_DEST = BASE_ADDR + 32’h20;
\nparameter CH2_DEST = BASE_ADDR + 32’h32;
\nparameter CH3_DEST = BASE_ADDR + 32’h44;<\/p>\n

\/\/ \u6d4b\u8bd5\u7528\u4f8b\u7f16\u53f7
\ninteger testcase;<\/p>\n

\/\/ \u8ba1\u6570\u5668
\nreg [7:0] cnt;<\/p>\n

\/\/ \u65f6\u949f\u3001\u590d\u4f4d
\nreg hreset_n, hclk;<\/p>\n

\/\/ ==============================<\/strong>
\n\/\/ AHB \u4e3b\u673a\u4fe1\u53f7\uff08\u6a21\u62df CPU\uff09<\/strong>
\n\/\/ ==============================<\/strong>
\nreg cpu_s_hsel; \/\/ \u7247\u9009
\nreg [31:0] cpu_s_haddr; \/\/ \u5730\u5740
\nreg [31:0] cpu_s_hwdata; \/\/ \u5199\u6570\u636e
\nreg cpu_s_hwrite; \/\/ \u8bfb\u5199
\nreg [1:0] cpu_s_htrans; \/\/ \u4f20\u8f93\u7c7b\u578b
\nreg [2:0] cpu_s_hburst; \/\/ \u7a81\u53d1\u7c7b\u578b
\nreg [2:0] cpu_s_hsize; \/\/ \u4f4d\u5bbd
\nreg [3:0] cpu_s_hprot; \/\/ \u4fdd\u62a4
\nreg cpu_s_hlock; \/\/ \u9501\u5b9a
\nreg cpu_s_hbusreq; \/\/ \u603b\u7ebf\u8bf7\u6c42<\/p>\n

\/\/ AHB \u8bfb\u6570\u636e\u3001DMA \u5c31\u7eea\u4fe1\u53f7
\nwire [31:0] hrdata;
\nwire hreadyout_from_dmaslv;<\/p>\n

\/\/ \u4e34\u65f6\u5bc4\u5b58\u5668
\nreg [31:0] xfr_reg;<\/p>\n

\/\/ ==============================<\/strong>
\n\/\/ \u5916\u8bbe DMA \u8bf7\u6c42\u89e6\u53d1\u4fe1\u53f7\uff08Testbench \u5185\u90e8\u7528\uff09<\/strong>
\n\/\/ ==============================<\/strong>
\nreg req_0_trig;
\nreg req_1_trig;
\nreg req_2_trig;
\nreg req_3_trig;<\/p>\n

\/\/ \u53d1\u7ed9 DMA \u7684\u5916\u8bbe\u8bf7\u6c42\u4fe1\u53f7\uff08peri_req = \u5916\u8bbe\u8bf7\u6c42DMA\uff09
\nreg peri_req_0;
\nreg peri_req_1;
\nreg peri_req_2;
\nreg peri_req_3;<\/p>\n

\/\/ DMA \u5e94\u7b54\u4fe1\u53f7\uff08DMA \u7ed9\u5916\u8bbe\u7684\u5e94\u7b54\uff09
\nwire dmac_ack_0;
\nwire dmac_ack_1;
\nwire dmac_ack_2;
\nwire dmac_ack_3;<\/p>\n

\/\/ \u6d4b\u8bd5\u7528\u901a\u9053\u4f7f\u80fd\/\u65b9\u5411
\nreg tb_ch_en_0;
\nreg tb_ch_en_1;
\nreg tb_ch_en_2;
\nreg tb_ch_en_3;<\/p>\n

reg tb_ch_tgt_0;
\nreg tb_ch_tgt_1;
\nreg tb_ch_tgt_2;
\nreg tb_ch_tgt_3;<\/p>\n

\/\/ \u6a21\u62df\u5916\u8bbe\u7ed9DMA\u7684\u6570\u636e
\nreg [31:0] tb_hrdatain;
\nreg [31:0] tb_ch_datain_0;
\nreg [31:0] tb_ch_datain_1;
\nreg [31:0] tb_ch_datain_2;
\nreg [31:0] tb_ch_datain_3;<\/p>\n

\/\/ ==============================<\/strong>
\n\/\/ \u5305\u542b AHB \u4eff\u771f\u4efb\u52a1\uff08\u5199\u3001\u8bfb\u3001\u7a7a\u95f2\uff09<\/strong>
\n\/\/ \u5c31\u662f\u4f60\u4e0a\u4e00\u4e2a\u6587\u4ef6 sim_ahb_task.v<\/strong>
\n\/\/ ==============================<\/strong>
\n`include “sim_ahb_task.v”<\/p>\n

\/\/ ==============================<\/strong>
\n\/\/ \u4f8b\u5316 DMA \u9876\u5c42\uff08\u88ab\u6d4b\u8bd5\u7684\u6a21\u5757\uff09<\/strong>
\n\/\/ ==============================<\/strong>
\ndmac u_dmac(
\n.HCLK (hclk),
\n.HRESETn (hreset_n),<\/p>\n

\/\/ AHB \u4ece\u673a\uff1aCPU \u914d\u7f6e\u63a5\u53e3
\n.HSEL_SLV (cpu_s_hsel),
\n.HREADYIN_SLV (1’b1),
\n.HTRANS_SLV (cpu_s_htrans),
\n.HSIZE_SLV (cpu_s_hsize),
\n.HWRITE_SLV (cpu_s_hwrite),
\n.HADDR_SLV (cpu_s_haddr),
\n.HWDATA_SLV (cpu_s_hwdata),
\n.HREADYOUT_SLV (hreadyout_from_dmaslv),
\n.HRESP_SLV (),
\n.HRDATA_SLV (hrdata),<\/p>\n

\/\/ AHB \u4e3b\u673a\uff1aDMA \u8bbf\u95ee\u603b\u7ebf\uff08\u4eff\u771f\u4e2d\u60ac\u7a7a\u4e0d\u63a5\uff09
\n.HSEL (),
\n.HTRANS (),
\n.HSIZE (),
\n.HWRITE (),
\n.HADDR (),
\n.HWDATA (),
\n.HREADY_IN (1’b1), \/\/ \u6a21\u62df\u4ece\u673a\u6c38\u8fdc\u5c31\u7eea
\n.HRESP (),
\n.HRDATA (tb_hrdatain), \/\/ \u6a21\u62df\u5916\u8bbe\u7ed9DMA\u7684\u6570\u636e<\/p>\n

\/\/ \u5916\u8bbe\u8bf7\u6c42 & DMA \u5e94\u7b54
\n.req_0 (peri_req_0),
\n.req_1 (peri_req_1),
\n.req_2 (peri_req_2),
\n.req_3 (peri_req_3),
\n.ack_0 (dmac_ack_0),
\n.ack_1 (dmac_ack_1),
\n.ack_2 (dmac_ack_2),
\n.ack_3 (dmac_ack_3)
\n);<\/p>\n

\/\/ ==============================<\/strong>
\n\/\/ \u5916\u8bbe\u8bf7\u6c42\u751f\u6210\u903b\u8f91\uff1atrig \u89e6\u53d1 \u2192 \u4ea7\u751f peri_req \u2192 \u6536\u5230 ack \u6e05\u9664<\/strong>
\n\/\/ \u4f5c\u7528\uff1a\u6a21\u62df\u5916\u8bbe\u201c\u6211\u9700\u8981DMA\u670d\u52a1\u201d<\/strong>
\n\/\/ ==============================<\/strong>
\nalways @(posedge hclk or negedge hreset_n)
\nif (!hreset_n) peri_req_0 <= 0;
\nelse if (req_0_trig)peri_req_0 <= 1;
\nelse if (dmac_ack_0)peri_req_0 <= 0;<\/p>\n

always @(posedge hclk or negedge hreset_n)
\nif (!hreset_n) peri_req_1 <= 0;
\nelse if (req_1_trig)peri_req_1 <= 1;
\nelse if (dmac_ack_1)peri_req_1 <= 0;<\/p>\n

always @(posedge hclk or negedge hreset_n)
\nif (!hreset_n) peri_req_2 <= 0;
\nelse if (req_2_trig)peri_req_2 <= 1;
\nelse if (dmac_ack_2)peri_req_2 <= 0;<\/p>\n

always @(posedge hclk or negedge hreset_n)
\nif (!hreset_n) peri_req_3 <= 0;
\nelse if (req_3_trig)peri_req_3 <= 1;
\nelse if (dmac_ack_3)peri_req_3 <= 0;<\/p>\n

\/\/ ==============================<\/strong>
\n\/\/ \u6a21\u62df\u5916\u8bbe\u53d1\u9001\u81ea\u589e\u6570\u636e\uff08\u6bcf\u89e6\u53d1\u4e00\u6b21+1\uff09<\/strong>
\n\/\/ \u4f5c\u7528\uff1a\u8ba9DMA\u642c\u7684\u6570\u636e\u6709\u89c4\u5f8b\uff0c\u65b9\u4fbf\u770b\u5bf9\u4e0d\u5bf9<\/strong>
\n\/\/ ==============================<\/strong>
\nalways @(posedge hclk or negedge hreset_n)
\nif (!hreset_n) tb_ch_datain_0 <= 0;
\nelse if (~tb_ch_en_0)tb_ch_datain_0 <= 0;
\nelse if (req_0_trig)tb_ch_datain_0 <= tb_ch_datain_0 + 1;<\/p>\n

always @(posedge hclk or negedge hreset_n)
\nif (!hreset_n) tb_ch_datain_1 <= 0;
\nelse if (~tb_ch_en_1)tb_ch_datain_1 <= 0;
\nelse if (req_0_trig)tb_ch_datain_1 <= tb_ch_datain_1 + 1;<\/p>\n

always @(posedge hclk or negedge hreset_n)
\nif (!hreset_n) tb_ch_datain_2 <= 0;
\nelse if (~tb_ch_en_2)tb_ch_datain_2 <= 0;
\nelse if (req_0_trig)tb_ch_datain_2 <= tb_ch_datain_2 + 1;<\/p>\n

always @(posedge hclk or negedge hreset_n)
\nif (!hreset_n) tb_ch_datain_3 <= 0;
\nelse if (~tb_ch_en_3)tb_ch_datain_3 <= 0;
\nelse if (req_0_trig)tb_ch_datain_3 <= tb_ch_datain_3 + 1;<\/p>\n

\/\/ ==============================<\/strong>
\n\/\/ \u6839\u636e\u5f53\u524d\u54ea\u4e2a\u5916\u8bbe\u8bf7\u6c42\uff0c\u628a\u5bf9\u5e94\u6570\u636e\u9001\u7ed9DMA\u7684HRDATA<\/strong>
\n\/\/ ==============================<\/strong>
\nalways @(posedge hclk or negedge hreset_n)
\nif (!hreset_n) tb_hrdatain <= 1;
\nelse if (peri_req_0) tb_hrdatain <= tb_ch_datain_0;
\nelse if (peri_req_1) tb_hrdatain <= tb_ch_datain_1;
\nelse if (peri_req_2) tb_hrdatain <= tb_ch_datain_2;
\nelse if (peri_req_3) tb_hrdatain <= tb_ch_datain_3;<\/p>\n

\/\/ ==============================<\/strong>
\n\/\/ \u65f6\u949f\u751f\u6210\uff1a100ns \u5468\u671f<\/strong>
\n\/\/ ==============================<\/strong>
\ninitial begin
\nforever #(PERIOD\/2) hclk = ~hclk;
\nend<\/p>\n

\/\/ ==============================<\/strong>
\n\/\/ \u4e3b\u6d4b\u8bd5\u6d41\u7a0b\uff08\u6838\u5fc3\uff01\uff09<\/strong>
\n\/\/ ==============================<\/strong>
\ninitial begin
\n\/\/ \u521d\u59cb\u5316\u4fe1\u53f7
\ntestcase = 0;
\nhreset_n = 1;
\nhclk = 1;
\nxfr_reg = 0;
\nreq_0_trig= 0;
\nreq_1_trig= 0;
\nreq_2_trig= 0;
\nreq_3_trig= 0;<\/p>\n

tb_ch_en_0=0;
\ntb_ch_en_1=0;
\ntb_ch_en_2=0;
\ntb_ch_en_3=0;<\/p>\n

tb_ch_tgt_0=0;
\ntb_ch_tgt_1=0;
\ntb_ch_tgt_2=0;
\ntb_ch_tgt_3=0;<\/p>\n

\/\/ \u590d\u4f4d
\n#(PERIOD*20) hreset_n = 0;
\n#(PERIOD*20) hreset_n = 1;<\/p>\n

\/\/ ————————–<\/strong>
\n\/\/ \u6d4b\u8bd5\u7528\u4f8b 1\uff1a\u5185\u5b58 \u2192 \u5916\u8bbe<\/strong>
\n\/\/ ————————–<\/strong>
\ntestcase = 1;<\/p>\n

\/\/ \u914d\u7f6e\u901a\u90530\u6e90\u5730\u5740
\n#(PERIOD*1) AHB_SIGNLE_WR(CH0_SOUR, 32’h4001_1000);
\n\/\/ \u914d\u7f6e\u901a\u90530\u76ee\u6807\u5730\u5740
\n#(PERIOD*1) AHB_SIGNLE_WR(CH0_DEST, 32’h4001_0000);
\n\/\/ \u914d\u7f6e\u901a\u90530\u63a7\u5236\u5bc4\u5b58\u5668\uff1a\u957f\u5ea6+\u4f7f\u80fd
\n#(PERIOD*1) AHB_SIGNLE_WR(CH0_CTRL, 32’h900 + CH0_EN);<\/p>\n

\/\/ \u6253\u5f00\u901a\u90530
\ntb_ch_en_0 = 1;
\ntb_ch_tgt_0 = 0;<\/p>\n

#(PERIOD*60);<\/p>\n

\/\/ \u89e6\u53d19\u6b21 DMA \u8bf7\u6c42
\nrepeat (9) begin
\n#(PERIOD*1) req_0_trig = 1;
\n#(PERIOD*1) req_0_trig = 0;
\n#(PERIOD*10);
\nend<\/p>\n

#(PERIOD*300);<\/p>\n

\/\/ \u590d\u4f4d
\n#(PERIOD*20) hreset_n = 0;
\n#(PERIOD*20) hreset_n = 1;<\/p>\n

\/\/ ————————–<\/strong>
\n\/\/ \u6d4b\u8bd5\u7528\u4f8b 2\uff1a\u5916\u8bbe \u2192 \u5185\u5b58<\/strong>
\n\/\/ ————————–<\/strong>
\ntestcase = 2;<\/p>\n

\/\/ \u914d\u7f6e\u901a\u90530
\n#(PERIOD*1) AHB_SIGNLE_WR(CH0_SOUR, 32’h4001_0000);
\n#(PERIOD*1) AHB_SIGNLE_WR(CH0_DEST, 32’h4001_1000);
\n#(PERIOD*1) AHB_SIGNLE_WR(CH0_CTRL, 32’ha00 + CH0_TGT + CH0_EN);<\/p>\n

tb_ch_en_0 = 1;
\ntb_ch_tgt_0 = 0;<\/p>\n

\/\/ \u89e6\u53d110\u6b21DMA\u8bf7\u6c42
\nrepeat (10) begin
\n#(PERIOD*1) req_0_trig = 1;
\n#(PERIOD*1) req_0_trig = 0;
\n#(PERIOD*20);
\nend<\/p>\n

#(PERIOD*300);<\/p>\n

\/\/ \u7ed3\u675f\u4eff\u771f
\n$finish;
\nend<\/p>\n

\/\/ ==============================<\/strong>
\n\/\/ \u6ce2\u5f62dump\uff1a\u4fdd\u5b58\u6ce2\u5f62\u6587\u4ef6\uff0c\u7528\u4e8eVerdi\u67e5\u770b<\/strong>
\n\/\/ ==============================<\/strong>
\ninitial begin
\n$fsdbDumpfile(“test_dma.fsdb”);
\n$fsdbDumpvars(0,”test_dma”);
\n$fsdbDumpMDA();
\nend<\/p>\n

endmodule<\/p>\n

\u4e09\u3001\u573a\u666f\u5316\u5927\u767d\u8bdd\uff08\u6700\u5173\u952e\uff09<\/strong>
\n\u628a test_dma.v \u60f3\u8c61\u6210\uff1a<\/strong>
\nDMA \u7684\u201c\u8003\u573a + \u76d1\u8003\u8001\u5e08 + \u5047\u5b66\u751f\u201d<\/strong>
\n\u2022 dmac\uff1a\u8003\u751f\uff08DMA \u63a7\u5236\u5668\uff09<\/strong>
\n\u2022 test_dma\uff1a\u8003\u573a<\/strong>
\n\u2022 AHB \u4efb\u52a1\uff1a\u5047 CPU\uff08\u8001\u5e08\u53d1\u5377\u5b50\uff09<\/strong>
\n\u2022 peri_req\uff1a\u5047\u5916\u8bbe\uff08\u5b66\u751f\u8981\u4ea4\u4f5c\u4e1a\uff09<\/strong>
\n\u2022 \u6ce2\u5f62\u6587\u4ef6\uff1a\u76d1\u63a7\u5f55\u50cf<\/strong><\/p>\n

\u6574\u4e2a\u8003\u8bd5\u6d41\u7a0b\uff1a<\/strong>
\n1. \u590d\u4f4d \u2192 \u8003\u751f\u5750\u597d<\/strong>
\n2. CPU \u914d\u7f6e DMA\uff08\u53d1\u5377\u5b50\uff09\uff1a<\/strong>
\n\u25e6 \u6e90\u5730\u5740<\/strong>
\n\u25e6 \u76ee\u6807\u5730\u5740<\/strong>
\n\u25e6 \u4f20\u8f93\u957f\u5ea6<\/strong>
\n\u25e6 \u542f\u52a8\u901a\u9053<\/strong>
\n3. \u6a21\u62df\u5916\u8bbe\u53d1\u8bf7\u6c42\uff1a\u6211\u8981\u4f20\u6570\u636e<\/strong>
\n4. DMA \u5e94\u7b54 + \u642c\u6570\u636e<\/strong>
\n5. \u770b\u6ce2\u5f62 \u5bf9\u4e0d\u5bf9<\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"

test_dma.v = DMA \u63a7\u5236\u5668\u7684\u4eff\u771f\u6d4b\u8bd5\u5e73\u53f0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2022 \u4f8b\u5316\u4f60\u524d\u9762\u7684 dmac \u9876\u5c42 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2022 \u7528 sim_ahb_task \u6a21\u62df CPU \u914d\u7f6e DMA \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2022 \u6a21\u62df \u5916\u8bbe\u89e6\u53d1 DMA \u8bf7\u6c42 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2022 \u81ea\u52a8\u8dd1\u6d4b\u8bd5\u7528\u4f8b\uff0c\u770b DMA \u642c\u6570\u636e\u5bf9\u4e0d\u5bf9 `timescale 1ns\/10ps \/\/ ============================== \/\/ \u6a21\u5757\uff1aDMA \u4eff\u771f\u6d4b\u8bd5\u9876\u5c42 \/\/ \u4f5c\u7528\uff1a\u7ed9DMA\u4f9b\u7535\u3001\u6a21\u62dfCPU\u3001\u6a21\u62df\u5916\u8bbe\u3001\u8dd1\u6d4b\u8bd5\u7528\u4f8b \/\/ ============================== module test_dma; \/\/ \u65f6\u949f\u5468\u671f\uff1a100ns \u2192 10MHz parameter PERIOD = 100; \/\/ DMA \u5bc4\u5b58\u5668\u57fa\u5730\u5740\uff08\u548c dmac_intf \u4e00\u81f4\uff09 parameter BASE_ADDR= 32’h4000_0000; \/\/ \u901a\u9053\u4f7f\u80fd parameter CH0_EN = 1; parameter CH1_EN = 1; parameter CH2_EN = 1; parameter CH3_EN = 1; \/\/ \u901a\u9053\u65b9\u5411\u914d\u7f6e parameter CH0_TGT = 32’h10; parameter CH1_TGT = 32’h10; parameter CH2_TGT = 32’h10; parameter CH3_TGT = 32’h10; \/\/ ============================== \/\/ DMA \u5bc4\u5b58\u5668\u5730\u5740\u6620\u5c04\uff08\u548c dmac_intf \u5b8c\u5168\u5bf9\u5e94\uff09 \/\/ ============================== parameter CH0_CTRL = BASE_ADDR + 32’h0; \/\/ \u901a\u90530\u63a7\u5236 parameter CH1_CTRL = BASE_ADDR + 32’h12; parameter CH2_CTRL = BASE_ADDR + 32’h24; parameter CH3_CTRL = BASE_ADDR + 32’h36; parameter CH0_SOUR = BASE_ADDR + 32’h4; \/\/ \u901a\u90530\u6e90\u5730\u5740 parameter CH1_SOUR = BASE_ADDR + 32’h16; parameter CH2_SOUR = BASE_ADDR + 32’h28; parameter CH3_SOUR = BASE_ADDR + 32’h40; parameter CH0_DEST = BASE_ADDR + 32’h8; \/\/ \u901a\u90530\u76ee\u6807\u5730\u5740 parameter CH1_DEST = BASE_ADDR + 32’h20; parameter CH2_DEST = BASE_ADDR + 32’h32; parameter CH3_DEST = BASE_ADDR + 32’h44; \/\/ \u6d4b\u8bd5\u7528\u4f8b\u7f16\u53f7 integer testcase; \/\/ \u8ba1\u6570\u5668 reg [7:0] cnt; \/\/ \u65f6\u949f\u3001\u590d\u4f4d reg hreset_n, hclk; \/\/ ============================== \/\/ AHB \u4e3b\u673a\u4fe1\u53f7\uff08\u6a21\u62df CPU\uff09 \/\/ ============================== reg cpu_s_hsel; \/\/ \u7247\u9009 reg [31:0] cpu_s_haddr; \/\/ \u5730\u5740 reg [31:0] cpu_s_hwdata; \/\/ \u5199\u6570\u636e reg cpu_s_hwrite; \/\/ \u8bfb\u5199 reg [1:0] cpu_s_htrans; \/\/ \u4f20\u8f93\u7c7b\u578b reg [2:0] cpu_s_hburst; \/\/ \u7a81\u53d1\u7c7b\u578b reg [2:0] cpu_s_hsize; \/\/ \u4f4d\u5bbd reg [3:0] cpu_s_hprot; \/\/ \u4fdd\u62a4 reg cpu_s_hlock; \/\/ \u9501\u5b9a reg cpu_s_hbusreq; \/\/ \u603b\u7ebf\u8bf7\u6c42 \/\/ AHB \u8bfb\u6570\u636e\u3001DMA \u5c31\u7eea\u4fe1\u53f7 wire [31:0] hrdata; wire hreadyout_from_dmaslv; \/\/ \u4e34\u65f6\u5bc4\u5b58\u5668 reg [31:0] xfr_reg; \/\/ ============================== \/\/ \u5916\u8bbe DMA \u8bf7\u6c42\u89e6\u53d1\u4fe1\u53f7\uff08Testbench \u5185\u90e8\u7528\uff09 \/\/ ===========================…<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-1430","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"_links":{"self":[{"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/posts\/1430","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/comments?post=1430"}],"version-history":[{"count":2,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/posts\/1430\/revisions"}],"predecessor-version":[{"id":1432,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/posts\/1430\/revisions\/1432"}],"wp:attachment":[{"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/media?parent=1430"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/categories?post=1430"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/tags?post=1430"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}