{"id":1426,"date":"2026-05-08T22:34:44","date_gmt":"2026-05-08T14:34:44","guid":{"rendered":"http:\/\/www.hanhhsir.cn\/?p=1426"},"modified":"2026-05-08T22:43:02","modified_gmt":"2026-05-08T14:43:02","slug":"%e5%9f%ba%e4%ba%8eahb%e7%9a%84%e5%9b%9b%e9%80%9a%e9%81%93dma%e6%8e%a7%e5%88%b6%e5%99%a8%e8%ae%be%e8%ae%a1-sim_ahb_task-v","status":"publish","type":"post","link":"http:\/\/www.hanhhsir.cn\/index.php\/2026\/05\/08\/%e5%9f%ba%e4%ba%8eahb%e7%9a%84%e5%9b%9b%e9%80%9a%e9%81%93dma%e6%8e%a7%e5%88%b6%e5%99%a8%e8%ae%be%e8%ae%a1-sim_ahb_task-v\/","title":{"rendered":"\u57fa\u4e8eAHB\u7684\u56db\u901a\u9053DMA\u63a7\u5236\u5668\u8bbe\u8ba1-sim_ahb_task.v"},"content":{"rendered":"<p><strong>sim_ahb_task.v = \u4eff\u771f\u7528AHB\u4e3b\u673a\u4efb\u52a1\u5e93<\/strong><br \/>\n<strong>\u4f5c\u7528\uff1a\u5728Testbench\u91cc\u6a21\u62dfCPU\uff0c\u901a\u8fc7AHB\u603b\u7ebf\u5bf9DMA\u8fdb\u884c\u5355\u6b21\u5199\u3001\u5355\u6b21\u8bfb\u3001\u7a7a\u95f2\u64cd\u4f5c\u3002<\/strong><br \/>\n<strong>\u5b83\u4e0d\u662fRTL\uff0c\u662f\u4eff\u771f\u6d4b\u8bd5\u4ee3\u7801\uff08Verilog Task\uff09\u3002<\/strong><\/p>\n<p><strong>\/\/ ==============================<\/strong><br \/>\n<strong>\/\/ \u529f\u80fd\uff1a\u4eff\u771fAHB\u4e3b\u673a\u4efb\u52a1<\/strong><br \/>\n<strong>\/\/ \u7528\u4e8eTestbench\u4e2d\u6a21\u62dfCPU\uff0c\u914d\u7f6e\/\u8bfb\u53d6DMA\u5bc4\u5b58\u5668<\/strong><br \/>\n<strong>\/\/ \u5305\u542b\uff1a\u5355\u6b21\u5199\u3001\u5355\u6b21\u8bfb\u3001\u7a7a\u95f2<\/strong><br \/>\n<strong>\/\/ ==============================<\/strong><\/p>\n<p><strong>\/\/ ==============================<\/strong><br \/>\n<strong>\/\/ Task 1\uff1aAHB \u5355\u6b21\u5199\u64cd\u4f5c\uff08CPU \u2192 DMA \u5199\u5bc4\u5b58\u5668\uff09<\/strong><br \/>\n<strong>\/\/ \u8f93\u5165\uff1a\u5730\u5740AHB_HADDR\u3001\u6570\u636eAHB_HWDATA<\/strong><br \/>\n<strong>\/\/ ==============================<\/strong><br \/>\ntask AHB_SIGNLE_WR;<br \/>\ninput [31:0] AHB_HADDR; \/\/ \u8981\u5199\u7684\u5730\u5740<br \/>\ninput [31:0] AHB_HWDATA; \/\/ \u8981\u5199\u7684\u6570\u636e<\/p>\n<p>begin<br \/>\n\/\/ 1. \u5730\u5740\u5468\u671f\uff1a\u53d1\u9001\u5730\u5740+\u63a7\u5236\u4fe1\u53f7<br \/>\nrepeat(1) @ (posedge hclk) \/\/ \u7b49\u5f851\u4e2a\u65f6\u949f\u6cbf<br \/>\nbegin<br \/>\ncpu_s_hsel &lt;= 1&#8217;b1; \/\/ \u9009\u4e2d\u4ece\u673a\uff08DMA\uff09<br \/>\ncpu_s_htrans &lt;= 2&#8217;b10; \/\/ \u975e\u5e8f\u5217\u4f20\u8f93\uff08NONSEQ\uff09<br \/>\ncpu_s_haddr &lt;= AHB_HADDR; \/\/ \u53d1\u5730\u5740<br \/>\ncpu_s_hburst &lt;= 0; \/\/ \u5355\u6b21\u4f20\u8f93<br \/>\ncpu_s_hwrite &lt;= 1; \/\/ \u5199\u64cd\u4f5c<br \/>\ncpu_s_hsize &lt;= 3&#8217;b010; \/\/ 32\u4f4d\u4f20\u8f93<br \/>\ncpu_s_hprot &lt;= 4&#8217;b1111; \/\/ \u6743\u9650\u6807\u8bb0<br \/>\nend<br \/>\n$display ($time,&#8221;&lt;WRITE START&gt;&#8221;); \/\/ \u6253\u5370\uff1a\u5199\u5f00\u59cb<\/p>\n<p>\/\/ 2. \u6570\u636e\u5468\u671f\uff1a\u7b49\u5f85\u4ece\u673a\u5c31\u7eea\uff0c\u53d1\u9001\u5199\u6570\u636e<br \/>\nrepeat (1) @ (posedge hclk)<br \/>\nbegin<br \/>\nwait (hreadyout_from_dmaslv == 1&#8217;b1); \/\/ \u7b49\u5f85DMA\u8fd4\u56de\u5c31\u7eea<\/p>\n<p>cpu_s_hwdata &lt;= AHB_HWDATA; \/\/ \u53d1\u9001\u6570\u636e<br \/>\ncpu_s_hsel &lt;= 1&#8217;b0 ; \/\/ \u53d6\u6d88\u9009\u4e2d<br \/>\ncpu_s_htrans &lt;= 2&#8217;b00 ; \/\/ \u56de\u5230IDLE<br \/>\ncpu_s_haddr &lt;= 32&#8217;h0 ; \/\/ \u5730\u5740\u6e05\u96f6<br \/>\ncpu_s_hburst &lt;= 3&#8217;b000 ;<br \/>\ncpu_s_hwrite &lt;= 1&#8217;b0 ;<br \/>\ncpu_s_hsize &lt;= 3&#8217;b010 ;<br \/>\ncpu_s_hprot &lt;= 4&#8217;b1111;<br \/>\ncpu_s_hbusreq &lt;= 1&#8217;b0 ;<br \/>\nend<\/p>\n<p>\/\/ 3. \u6570\u636e\u6e05\u96f6<br \/>\nrepeat (1) @ (posedge hclk)<br \/>\ncpu_s_hwdata &lt;= 32&#8217;h0;<\/p>\n<p>$display($time,&#8221; &lt;write done &gt;&#8221;); \/\/ \u6253\u5370\uff1a\u5199\u5b8c\u6210<br \/>\nend<br \/>\nendtask<\/p>\n<p><strong>\/\/ ==============================<\/strong><br \/>\n<strong>\/\/ Task 2\uff1aAHB \u7a7a\u95f2\u72b6\u6001\uff08\u603b\u7ebf\u7a7a\u95f2\uff09<\/strong><br \/>\n<strong>\/\/ ==============================<\/strong><br \/>\ntask AHB_IDLE ;<br \/>\nbegin<br \/>\ncpu_s_hlock &lt;= 1&#8217;b0 ;<br \/>\ncpu_s_htrans &lt;= 2&#8217;b00 ; \/\/ IDLE \u65e0\u4f20\u8f93<br \/>\ncpu_s_haddr &lt;= 32&#8217;h0000;<br \/>\ncpu_s_hburst &lt;= 3&#8217;b000 ;<br \/>\ncpu_s_hwrite &lt;= 1&#8217;b0 ;<br \/>\ncpu_s_hbusreq &lt;= 1&#8217;b0 ;<br \/>\ncpu_s_hsize &lt;= 3&#8217;b010 ; \/\/ 32\u4f4d<br \/>\ncpu_s_hprot &lt;= 4&#8217;b1111 ;<br \/>\ncpu_s_hwdata &lt;= 32&#8217;h0000 ;<br \/>\nend<br \/>\nendtask<\/p>\n<p><strong>\/\/ ==============================<\/strong><br \/>\n<strong>\/\/ Task 3\uff1aAHB \u5355\u6b21\u8bfb\u64cd\u4f5c\uff08CPU \u2190 DMA \u8bfb\u5bc4\u5b58\u5668\uff09<\/strong><br \/>\n<strong>\/\/ \u8f93\u5165\uff1a\u5730\u5740AHB_HADDR<\/strong><br \/>\n<strong>\/\/ \u8f93\u51fa\uff1a\u8bfb\u5230\u7684\u6570\u636eAHB_HRDATA<\/strong><br \/>\n<strong>\/\/ ==============================<\/strong><br \/>\ntask AHB_SIGNLE_RD ;<br \/>\ninput [31:0] AHB_HADDR ; \/\/ \u8bfb\u5730\u5740<br \/>\noutput [31:0] AHB_HRDATA ; \/\/ \u8bfb\u51fa\u7684\u6570\u636e<\/p>\n<p>begin<br \/>\n\/\/ 1. \u5730\u5740\u5468\u671f\uff1a\u53d1\u5730\u5740+\u8bfb\u63a7\u5236<br \/>\nrepeat (1) @ (posedge hclk);<br \/>\nbegin<br \/>\ncpu_s_hsel &lt;= 1&#8217;b1 ; \/\/ \u9009\u4e2dDMA<br \/>\ncpu_s_htrans &lt;= 2&#8217;b10 ; \/\/ NONSEQ<br \/>\ncpu_s_haddr &lt;= AHB_HADDR ; \/\/ \u5730\u5740<br \/>\ncpu_s_hburst &lt;= 3&#8217;b000 ; \/\/ \u5355\u6b21<br \/>\ncpu_s_hwrite &lt;= 1&#8217;b0 ; \/\/ \u8bfb\u64cd\u4f5c<br \/>\ncpu_s_hsize &lt;= 3&#8217;b010 ; \/\/ 32\u4f4d<br \/>\ncpu_s_hprot &lt;= 4&#8217;b1111 ;<br \/>\nend<\/p>\n<p>\/\/ 2. \u7b49\u5f85\u4f20\u8f93<br \/>\nrepeat (1) @ (posedge hclk);<br \/>\n$display(&#8221; &lt; read start &gt;&#8221;);<\/p>\n<p>\/\/ 3. \u6570\u636e\u5468\u671f\uff1a\u7b49\u5f85\u5c31\u7eea\uff0c\u8bfb\u53d6\u6570\u636e<br \/>\nrepeat (1) @ (posedge hclk);<br \/>\nbegin<br \/>\nwait (hreadyout_from_dmaslv == 1&#8217;b1); \/\/ \u7b49DMA\u5c31\u7eea<\/p>\n<p>AHB_HRDATA = hrdata ; \/\/ \u628a\u603b\u7ebf\u4e0a\u7684\u6570\u636e\u8bfb\u51fa\u6765<\/p>\n<p>\/\/ \u603b\u7ebf\u56de\u5230\u7a7a\u95f2<br \/>\ncpu_s_hsel &lt;= 1&#8217;b0 ;<br \/>\ncpu_s_htrans &lt;= 2&#8217;b00 ;<br \/>\ncpu_s_haddr &lt;= 32&#8217;h0000 ;<br \/>\ncpu_s_hburst &lt;= 3&#8217;b000 ;<br \/>\ncpu_s_hwrite &lt;= 1&#8217;b0 ;<br \/>\ncpu_s_hsize &lt;= 3&#8217;b010 ;<br \/>\ncpu_s_hprot &lt;= 4&#8217;b1111 ;<br \/>\ncpu_s_hwdata &lt;= 32&#8217;h0000 ;<br \/>\ncpu_s_hbusreq &lt;= 1&#8217;b0 ;<\/p>\n<p>$display($time, &#8220;&lt; read done &gt;&#8221;);<br \/>\n\/\/ \u6ce8\uff1a\u539f\u4ee3\u7801\u5199\u9519\u6210write done\uff0c\u5e94\u4e3aread done<br \/>\nend<br \/>\nend<br \/>\nendtask<\/p>\n<p><strong>\u4e03\u3001\u548c\u4f60\u6574\u5957DMA\u7684\u5173\u7cfb<\/strong><br \/>\n<strong>1. sim_ahb_task\uff08\u5047CPU\uff09<\/strong><br \/>\n<strong>2. \u2192 \u901a\u8fc7AHB\u5199 dmac_intf\uff08\u914d\u7f6e\u63a5\u53e3\uff09<\/strong><br \/>\n<strong>3. \u2192 dmac_arb \u4ef2\u88c1<\/strong><br \/>\n<strong>4. \u2192 dmac_ahb_ctrl \u53d1\u603b\u7ebf\u4f20\u8f93<\/strong><br \/>\n<strong>5. \u2192 \u5b8c\u6210DMA\u642c\u8fd0<\/strong><br \/>\n<strong>\u5b83\u662f\u4f60\u4eff\u771f\u9a8c\u8bc1DMA\u7684\u5fc5\u5907\u5de5\u5177\uff01<\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"<p>sim_ahb_task.v = \u4eff\u771f\u7528AHB\u4e3b\u673a\u4efb\u52a1\u5e93 \u4f5c\u7528\uff1a\u5728Testbench\u91cc\u6a21\u62dfCPU\uff0c\u901a\u8fc7AHB\u603b\u7ebf\u5bf9DMA\u8fdb\u884c\u5355\u6b21\u5199\u3001\u5355\u6b21\u8bfb\u3001\u7a7a\u95f2\u64cd\u4f5c\u3002 \u5b83\u4e0d\u662fRTL\uff0c\u662f\u4eff\u771f\u6d4b\u8bd5\u4ee3\u7801\uff08Verilog Task\uff09\u3002 \/\/ ============================== \/\/ \u529f\u80fd\uff1a\u4eff\u771fAHB\u4e3b\u673a\u4efb\u52a1 \/\/ \u7528\u4e8eTestbench\u4e2d\u6a21\u62dfCPU\uff0c\u914d\u7f6e\/\u8bfb\u53d6DMA\u5bc4\u5b58\u5668 \/\/ \u5305\u542b\uff1a\u5355\u6b21\u5199\u3001\u5355\u6b21\u8bfb\u3001\u7a7a\u95f2 \/\/ ============================== \/\/ ============================== \/\/ Task 1\uff1aAHB \u5355\u6b21\u5199\u64cd\u4f5c\uff08CPU \u2192 DMA \u5199\u5bc4\u5b58\u5668\uff09 \/\/ \u8f93\u5165\uff1a\u5730\u5740AHB_HADDR\u3001\u6570\u636eAHB_HWDATA \/\/ ============================== task AHB_SIGNLE_WR; input [31:0] AHB_HADDR; \/\/ \u8981\u5199\u7684\u5730\u5740 input [31:0] AHB_HWDATA; \/\/ \u8981\u5199\u7684\u6570\u636e begin \/\/ 1. \u5730\u5740\u5468\u671f\uff1a\u53d1\u9001\u5730\u5740+\u63a7\u5236\u4fe1\u53f7 repeat(1) @ (posedge hclk) \/\/ \u7b49\u5f851\u4e2a\u65f6\u949f\u6cbf begin cpu_s_hsel &lt;= 1&#8217;b1; \/\/ \u9009\u4e2d\u4ece\u673a\uff08DMA\uff09 cpu_s_htrans &lt;= 2&#8217;b10; \/\/ \u975e\u5e8f\u5217\u4f20\u8f93\uff08NONSEQ\uff09 cpu_s_haddr &lt;= AHB_HADDR; \/\/ \u53d1\u5730\u5740 cpu_s_hburst &lt;= 0; \/\/ \u5355\u6b21\u4f20\u8f93 cpu_s_hwrite &lt;= 1; \/\/ \u5199\u64cd\u4f5c cpu_s_hsize &lt;= 3&#8217;b010; \/\/ 32\u4f4d\u4f20\u8f93 cpu_s_hprot &lt;= 4&#8217;b1111; \/\/ \u6743\u9650\u6807\u8bb0 end $display ($time,&#8221;&lt;WRITE START&gt;&#8221;); \/\/ \u6253\u5370\uff1a\u5199\u5f00\u59cb \/\/ 2. \u6570\u636e\u5468\u671f\uff1a\u7b49\u5f85\u4ece\u673a\u5c31\u7eea\uff0c\u53d1\u9001\u5199\u6570\u636e repeat (1) @ (posedge hclk) begin wait (hreadyout_from_dmaslv == 1&#8217;b1); \/\/ \u7b49\u5f85DMA\u8fd4\u56de\u5c31\u7eea cpu_s_hwdata &lt;= AHB_HWDATA; \/\/ \u53d1\u9001\u6570\u636e cpu_s_hsel &lt;= 1&#8217;b0 ; \/\/ \u53d6\u6d88\u9009\u4e2d cpu_s_htrans &lt;= 2&#8217;b00 ; \/\/ \u56de\u5230IDLE cpu_s_haddr &lt;= 32&#8217;h0 ; \/\/ \u5730\u5740\u6e05\u96f6 cpu_s_hburst &lt;= 3&#8217;b000 ; cpu_s_hwrite &lt;= 1&#8217;b0 ; cpu_s_hsize &lt;= 3&#8217;b010 ; cpu_s_hprot &lt;= 4&#8217;b1111; cpu_s_hbusreq &lt;= 1&#8217;b0 ; end \/\/ 3. \u6570\u636e\u6e05\u96f6 repeat (1) @ (posedge hclk) cpu_s_hwdata &lt;= 32&#8217;h0; $display($time,&#8221; &lt;write done &gt;&#8221;); \/\/ \u6253\u5370\uff1a\u5199\u5b8c\u6210 end endtask \/\/ ============================== \/\/ Task 2\uff1aAHB \u7a7a\u95f2\u72b6\u6001\uff08\u603b\u7ebf\u7a7a\u95f2\uff09 \/\/ ============================== task AHB_IDLE ; begin cpu_s_hlock &lt;= 1&#8217;b0 ; cpu_s_htrans &lt;= 2&#8217;b00 ; \/\/ IDLE \u65e0\u4f20\u8f93 cpu_s_haddr &lt;= 32&#8217;h0000; cpu_s_hburst &lt;= 3&#8217;b000 ; cpu_s_hwrite &lt;= 1&#8217;b0 ; cpu_s_hbusreq &lt;= 1&#8217;b0 ; cpu_s_hsize &lt;= 3&#8217;b010 ; \/\/ 32\u4f4d cpu_s_hprot &lt;= 4&#8217;b1111 ; cpu_s_hwdata &lt;= 32&#8217;h0000 ; end endtask \/\/ ============================== \/\/ Task 3\uff1aAHB \u5355\u6b21\u8bfb\u64cd\u4f5c\uff08CPU \u2190 DMA \u8bfb\u5bc4\u5b58\u5668\uff09 \/\/ \u8f93\u5165\uff1a\u5730\u5740AHB_HADDR \/\/ \u8f93\u51fa\uff1a\u8bfb\u5230\u7684\u6570&#8230;<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-1426","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"_links":{"self":[{"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/posts\/1426","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/comments?post=1426"}],"version-history":[{"count":2,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/posts\/1426\/revisions"}],"predecessor-version":[{"id":1433,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/posts\/1426\/revisions\/1433"}],"wp:attachment":[{"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/media?parent=1426"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/categories?post=1426"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/tags?post=1426"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}