{"id":1402,"date":"2026-05-08T14:41:20","date_gmt":"2026-05-08T06:41:20","guid":{"rendered":"http:\/\/www.hanhhsir.cn\/?p=1402"},"modified":"2026-05-08T21:35:12","modified_gmt":"2026-05-08T13:35:12","slug":"%e5%9f%ba%e4%ba%8eahb%e7%9a%84%e5%9b%9b%e9%80%9a%e9%81%93dma%e6%8e%a7%e5%88%b6%e5%99%a8%e8%ae%be%e8%ae%a1-dma%e7%9a%844%e9%80%9a%e9%81%93%e6%8e%a7%e5%88%b6","status":"publish","type":"post","link":"http:\/\/www.hanhhsir.cn\/index.php\/2026\/05\/08\/%e5%9f%ba%e4%ba%8eahb%e7%9a%84%e5%9b%9b%e9%80%9a%e9%81%93dma%e6%8e%a7%e5%88%b6%e5%99%a8%e8%ae%be%e8%ae%a1-dma%e7%9a%844%e9%80%9a%e9%81%93%e6%8e%a7%e5%88%b6\/","title":{"rendered":"\u57fa\u4e8eAHB\u7684\u56db\u901a\u9053DMA\u63a7\u5236\u5668\u8bbe\u8ba1-dmac_channel_ctrl.v"},"content":{"rendered":"
dmac_channel_ctrl = DMA \u52a9\u7406\u7684 \u201c\u603b\u8c03\u5ea6\u5458\u201d<\/strong><\/span><\/div>\n
    \n
  • \u7ba1 4 \u4e2a\u901a\u9053\u30014 \u4e2a\u8d27\u67b6<\/span><\/li>\n
  • \u7ba1\u6e90\u5730\u5740\u3001\u76ee\u6807\u5730\u5740\u3001\u642c\u8fd0\u957f\u5ea6<\/span><\/li>\n
  • \u7ba1\u4ec0\u4e48\u65f6\u5019\u8bfb\u3001\u4ec0\u4e48\u65f6\u5019\u5199<\/span><\/li>\n
  • \u7ba1 FIFO \u4ec0\u4e48\u65f6\u5019\u653e\u8d27\u3001\u4ec0\u4e48\u65f6\u5019\u53d6\u8d27<\/span><\/li>\n
  • \u6307\u6325 AHB \u63a7\u5236\u5668\u53bb\u4e3b\u5e72\u9053\u8fd0\u8f93<\/span><\/li>\n<\/ul>\n

    dmac_channel_ctrl \u662f DMA \u7684 4 \u901a\u9053\u603b\u8c03\u5ea6\u5458\u3002\u8001\u5e08\uff08CPU\uff09\u4e0b\u8fbe\u4efb\u52a1\u540e\uff0c\u8c03\u5ea6\u5458\u6839\u636e\u6e90\u5730\u5740\u3001\u76ee\u6807\u5730\u5740\u3001\u642c\u8fd0\u957f\u5ea6\uff0c\u63a7\u5236\u4e24\u4e2a\u72b6\u6001\u673a\u5206\u522b\u5904\u7406 \u201c\u5185\u5b58\u2192\u5916\u8bbe\u201d \u548c \u201c\u5916\u8bbe\u2192\u5185\u5b58\u201d \u4e24\u79cd\u642c\u8fd0\u65b9\u5411\uff0c\u81ea\u52a8\u5730\u5740\u81ea\u589e\u3001\u8ba1\u6570\u3001\u5224\u65ad FIFO \u7a7a\u6ee1\uff0c\u6307\u6325 AHB \u63a7\u5236\u5668\u5b8c\u6210\u8fd0\u8f93\uff0c\u5e76\u628a\u5feb\u9012\u6682\u5b58\u5230\u5bf9\u5e94\u8d27\u67b6\uff0c\u4efb\u52a1\u5b8c\u6210\u540e\u901a\u77e5\u7cfb\u7edf\u3002\u6574\u4e2a\u8fc7\u7a0b\u5168\u81ea\u52a8\uff0c\u4e0d\u7528\u8001\u5e08\u63d2\u624b\u3002<\/strong><\/span><\/p>\n

    `timescale 1ns\/10ps<\/span><\/p>\n

    \/\/ ==============================<\/span><\/strong>
    \n\/\/ \u6a21\u5757\uff1admac_channel_ctrl<\/span><\/strong>
    \n\/\/ \u529f\u80fd\uff1aDMA 4\u901a\u9053\u603b\u63a7\u5236\u5668\uff08\u603b\u8c03\u5ea6\u5458\uff09<\/span><\/strong>
    \n\/\/ \u573a\u666f\uff1a\u3010\u52a9\u7406\u624b\u4e0b\u7684\u5feb\u9012\u603b\u8c03\u5ea6\u3011<\/span><\/strong>
    \n\/\/ \u4f5c\u7528\uff1a\u7edf\u4e00\u7ba1\u74064\u8def\u65e0\u4eba\u673a\u8fd0\u8f93\uff0c\u63a7\u5236\u5730\u5740\u3001\u8ba1\u6570\u3001FIFO\u3001\u72b6\u6001\u673a<\/span><\/strong>
    \n\/\/ ==============================<\/span><\/strong><\/p>\n

    module dmac_channel_ctrl(<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 input clk, \/\/ \u5de5\u4f5c\u8282\u62cd<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 input rst, \/\/ \u7cfb\u7edf\u590d\u4f4d\uff0c\u5168\u90e8\u91cd\u6765<\/span><\/p>\n

    \/\/ 4\u4e2a\u901a\u9053\u7684\u8bf7\u6c42\u4fe1\u53f7\uff1a\u8c01\u8981\u5e72\u6d3b<\/span>
    \ninput req_0, req_1, req_2, req_3,<\/span><\/p>\n

    \/\/ \u5bf9\u63a5AHB\u63a7\u5236\u5668\uff08\u9053\u8def\u7ba1\u7406\u5458\uff09<\/span>
    \noutput wr, \/\/ \u5199\u547d\u4ee4\uff1a\u9001\u5feb\u9012<\/span>
    \noutput rd, \/\/ \u8bfb\u547d\u4ee4\uff1a\u53d6\u5feb\u9012<\/span>
    \noutput [31:0] addr, \/\/ \u5730\u5740\uff1a\u53bb\u54ea\u53d6\/\u9001\u5230\u54ea<\/span>
    \noutput [31:0] wdata, \/\/ \u8981\u9001\u7684\u5feb\u9012<\/span>
    \ninput [31:0] rdata, \/\/ \u53d6\u56de\u6765\u7684\u5feb\u9012<\/span>
    \ninput rd_en, \/\/ \u53d6\u5230\u6709\u6548\u5feb\u9012<\/span><\/p>\n

    \/\/ \u901a\u9053\u4f7f\u80fd\uff1a\u54ea\u4e2a\u901a\u9053\u542f\u52a8<\/span>
    \ninput en_0,en_1,en_2,en_3,<\/span><\/p>\n

    \/\/ \u4f20\u8f93\u65b9\u5411\uff1a0=\u5185\u5b58\u2192\u5916\u8bbe 1=\u5916\u8bbe\u2192\u5185\u5b58<\/span>
    \ninput target_0,target_1,target_2,target_3,<\/span><\/p>\n

    \/\/ \u6bcf\u4e2a\u901a\u9053\u8981\u642c\u591a\u5c11\u5feb\u9012<\/span>
    \ninput [9:0] ch_0_size,ch_1_size,ch_2_size,ch_3_size,<\/span><\/p>\n

    \/\/ \u6e90\u5730\u5740\u3001\u76ee\u6807\u5730\u5740<\/span>
    \ninput [31:0] ch_0_sour,ch_0_dest,<\/span>
    \ninput [31:0] ch_1_sour,ch_1_dest,<\/span>
    \ninput [31:0] ch_2_sour,ch_2_dest,<\/span>
    \ninput [31:0] ch_3_sour,ch_3_dest,<\/span><\/p>\n

    \/\/ FIFO\u7a7a\/\u6ee1\u72b6\u6001<\/span>
    \ninput fifo_0_empty,fifo_1_empty,fifo_2_empty,fifo_3_empty,<\/span>
    \ninput fifo_0_full,fifo_1_full,fifo_2_full,fifo_3_full,<\/span><\/p>\n

    \/\/ \u63a7\u5236FIFO\uff1a\u653e\u5feb\u9012\u3001\u53d6\u5feb\u9012<\/span>
    \noutput wr_fifo_0, wr_fifo_data_0, rd_fifo_0,<\/span>
    \ninput [31:0] rd_fifo_data_0,<\/span><\/p>\n

    output wr_fifo_1, wr_fifo_data_1, rd_fifo_1,<\/span>
    \ninput [31:0] rd_fifo_data_1,<\/span><\/p>\n

    output wr_fifo_2, wr_fifo_data_2, rd_fifo_2,<\/span>
    \ninput [31:0] rd_fifo_data_2,<\/span><\/p>\n

    output wr_fifo_3, wr_fifo_data_3, rd_fifo_3,<\/span>
    \ninput [31:0] rd_fifo_data_3,<\/span><\/p>\n

    input hready_in, \/\/ \u5bf9\u65b9\u5df2\u5c31\u7eea<\/span>
    \noutput req_done, \/\/ \u672c\u6b21\u4f20\u8f93\u5b8c\u6210<\/span><\/p>\n

    \/\/ 4\u4e2a\u901a\u9053\u4efb\u52a1\u5b8c\u6210\u6807\u5fd7<\/span>
    \noutput reg ch_0_t0_done,<\/span>
    \noutput reg ch_1_t0_done,<\/span>
    \noutput reg ch_2_t0_done,<\/span>
    \noutput reg ch_3_t0_done<\/span>
    \n);<\/span><\/p>\n

    parameter MAX_TRANS=8; \/\/ \u4e00\u6b21\u6700\u591a\u642c8\u4e2a<\/span>
    \nparameter TRANS_W=3;<\/span><\/p>\n

    \/\/ \u6bcf\u4e2a\u901a\u9053\u5df2\u642c\u8fd0\u8ba1\u6570<\/span>
    \nreg [9:0] cnt_t0_0,cnt_t0_1,cnt_t0_2,cnt_t0_3;<\/span><\/p>\n

    reg [TRANS_W-1:0] t0_cnt; \/\/ \u7a81\u53d1\u4f20\u8f93\u8ba1\u6570\u5668<\/span>
    \nwire t0_mt_done; \/\/ \u4e00\u6b21\u7a81\u53d1\u5b8c\u6210<\/span><\/p>\n

    \/\/ \u65b9\u54110\uff1a\u5185\u5b58 \u2192 \u5916\u8bbe\uff08\u53d6\u5feb\u9012\u2192\u9001\u529e\u516c\u5ba4\uff09<\/span>
    \nwire peri_t0_req;<\/span>
    \nwire mem_t0_req;<\/span><\/p>\n

    \/\/ \u65b9\u54111\uff1a\u5916\u8bbe \u2192 \u5185\u5b58\uff08\u529e\u516c\u5ba4\u2192\u9001\u56de\u5feb\u9012\u70b9\uff09<\/span>
    \nwire peri_t1_req;<\/span>
    \nwire mem_t1_req;<\/span><\/p>\n

    \/\/ \u901a\u9053\u4f7f\u80fd<\/span>
    \nwire ch0_t0_en,ch1_t0_en,ch2_t0_en,ch3_t0_en;<\/span>
    \nwire ch0_t1_en,ch1_t1_en,ch2_t1_en,ch3_t1_en;<\/span><\/p>\n

    \/\/ \u5730\u5740\u5bc4\u5b58\u5668<\/span>
    \nreg [31:0] rd_addr_0,rd_addr_1,rd_addr_2,rd_addr_3;<\/span>
    \nwire [31:0] t0_rm_addr; \/\/ \u8bfb\u5185\u5b58\u5730\u5740<\/span>
    \nwire [31:0] t0_wp_addr; \/\/ \u5199\u5916\u8bbe\u5730\u5740<\/span>
    \nreg t0_wr,t0_rd; \/\/ \u65b9\u54110\u8bfb\u5199<\/span><\/p>\n

    wire t0_done; \/\/ \u65b9\u54110\u5168\u90e8\u5b8c\u6210<\/span><\/p>\n

    wire [31:0] t1_rp_addr; \/\/ \u8bfb\u5916\u8bbe\u5730\u5740<\/span>
    \nwire [31:0] t1_wm_addr; \/\/ \u5199\u5185\u5b58\u5730\u5740<\/span>
    \nreg t1_wr,t1_rd; \/\/ \u65b9\u54111\u8bfb\u5199<\/span><\/p>\n

    \/\/ FIFO\u63a7\u5236<\/span>
    \nwire wr_fifo;<\/span>
    \nwire [31:0] wr_fifo_data;<\/span>
    \nwire rd_fifo;<\/span><\/p>\n

    \/\/ \u4f7f\u80fd\u5ef6\u65f6<\/span>
    \nreg en_0_d,en_1_d,en_2_d,en_3_d;<\/span>
    \nwire en_0_r,en_1_r,en_2_r,en_3_r;<\/span>
    \nreg en_0_r_d,en_1_r_d,en_2_r_d,en_3_r_d;<\/span><\/p>\n

    reg [31:0] rd_addr_t1_0,rd_addr_t1_1,rd_addr_t1_2,rd_addr_t1_3;<\/span><\/p>\n

    \/\/ ==============================<\/span><\/strong>
    \n\/\/ \u65b9\u54110\u72b6\u6001\u673a\uff1a\u5185\u5b58 \u2192 \u5916\u8bbe\uff08\u53d6\u5feb\u9012\u2192\u9001\u529e\u516c\u5ba4\uff09<\/span><\/strong>
    \n\/\/ ==============================<\/span><\/strong>
    \nreg [5:0] s0_cs; \/\/ \u5f53\u524d\u72b6\u6001<\/span>
    \nreg [5:0] s0_ns; \/\/ \u4e0b\u4e00\u72b6\u6001<\/span><\/p>\n

    parameter S0_IDLE = 6’b000000; \/\/ \u7a7a\u95f2<\/span>
    \nparameter S0_R_M = 6’b000001; \/\/ \u8bfb\u5185\u5b58\uff08\u53d6\u5feb\u9012\uff09<\/span>
    \nparameter S0_WAIT_R = 6’b000010; \/\/ \u7b49\u5f85\u53d6\u5230<\/span>
    \nparameter S0_W_P = 6’b000100; \/\/ \u5199\u5916\u8bbe\uff08\u9001\u529e\u516c\u5ba4\uff09<\/span>
    \nparameter S0_WAIT_W = 6’b001000; \/\/ \u7b49\u5f85\u9001\u5230<\/span><\/p>\n

    \/\/ \u901a\u90530~3\u65b9\u54110\u4f7f\u80fd<\/span>
    \nassign ch0_t0_en=en_0 && target_0==0;<\/span>
    \nassign ch1_t0_en=en_1 && target_1==0;<\/span>
    \nassign ch2_t0_en=en_2 && target_2==0;<\/span>
    \nassign ch3_t0_en=en_3 && target_3==0;<\/span><\/p>\n

    \/\/ \u5916\u8bbe\u8bf7\u6c42\uff1aFIFO\u975e\u7a7a\uff0c\u53ef\u4ee5\u9001<\/span>
    \nassign peri_t0_req =(req_0&&ch0_t0_en&&fifo_0_empty==0)||<\/span>
    \n(req_1&&ch1_t0_en&&fifo_1_empty==0)||<\/span>
    \n(req_2&&ch2_t0_en&&fifo_2_empty==0)||<\/span>
    \n(req_3&&ch3_t0_en&&fifo_3_empty==0);<\/span><\/p>\n

    \/\/ \u5185\u5b58\u8bf7\u6c42\uff1a\u9700\u8981\u53d6\u5feb\u9012<\/span>
    \nassign mem_t0_req=(ch0_t0_en|ch1_t0_en|ch2_t0_en|ch3_t0_en)&&~t0_done;<\/span><\/p>\n

    \/\/ \u72b6\u6001\u673a\u65f6\u5e8f\u903b\u8f91<\/span>
    \nalways @(posedge clk or negedge rst)<\/span>
    \nif (!rst) s0_cs<=S0_IDLE;<\/span>
    \nelse s0_cs<=s0_ns;<\/span><\/p>\n

    \/\/ \u72b6\u6001\u673a\u7ec4\u5408\u903b\u8f91<\/span><\/strong>
    \nalways @(*)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 case (s0_cs)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 S0_IDLE: begin<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (peri_t0_req) s0_ns=S0_W_P; \/\/ \u9001\u5feb\u9012<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else if (mem_t0_req) s0_ns=S0_R_M; \/\/ \u53d6\u5feb\u9012<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else s0_ns=S0_IDLE;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 end<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 S0_R_M: s0_ns=S0_WAIT_R; \/\/ \u53d6\u8d27\u540e\u7b49\u5f85<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 S0_WAIT_R: begin<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (rd_en && (t0_mt_done||t0_done)) s0_ns=S0_IDLE;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else if (rd_en && ~t0_mt_done) s0_ns=S0_R_M;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else s0_ns=S0_WAIT_R;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0end<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0S0_W_P: s0_ns=S0_WAIT_W; \/\/ \u9001\u8d27<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0S0_WAIT_W: s0_ns=hready_in ? S0_IDLE : S0_WAIT_W;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0default : s0_ns=S0_IDLE;<\/span><\/p>\n

    \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 endcase<\/span><\/p>\n

    \/\/ \u901a\u90530\u642c\u8fd0\u8ba1\u6570<\/span>
    \nalways @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (!rst) cnt_t0_0<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else if (target_0) cnt_t0_0<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else if (en_0 && s0_cs==S0_R_M) cnt_t0_0<=cnt_t0_0+1;<\/span><\/p>\n

    \/\/ \u901a\u90531\/2\/3\u8ba1\u6570\uff08\u903b\u8f91\u4e00\u6837\uff09<\/span>
    \nalways @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (!rst) cnt_t0_1<=0; else if (target_1) cnt_t0_1<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else if (en_1 && s0_cs==S0_R_M) cnt_t0_1<=cnt_t0_1+1;<\/span><\/p>\n

    always @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0if (!rst) cnt_t0_2<=0; else if (target_2) cnt_t0_2<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0else if (en_2 && s0_cs==S0_R_M) cnt_t0_2<=cnt_t0_2+1;<\/span><\/p>\n

    always @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0if (!rst) cnt_t0_3<=0; else if (target_3) cnt_t0_3<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0else if (en_3 && s0_cs==S0_R_M) cnt_t0_3<=cnt_t0_3+1;<\/span><\/p>\n

    \/\/ \u7a81\u53d1\u4f20\u8f93\u8ba1\u6570\u5668<\/span>
    \nalways @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0if (!rst) t0_cnt<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0else if (s0_cs==S0_IDLE) t0_cnt<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0else if(s0_cs==S0_R_M) t0_cnt<=t0_cnt+1;<\/span><\/p>\n

    assign t0_mt_done = t0_cnt==0 && s0_cs==S0_WAIT_R;<\/span><\/p>\n

    \/\/ \u901a\u90530~3\u4efb\u52a1\u5b8c\u6210\u6807\u5fd7<\/span>
    \nalways @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0if (!rst) ch_0_t0_done<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0else if (en_0 && target_0==0 && cnt_t0_0==ch_0_size)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0ch_0_t0_done<=1;<\/span><\/p>\n

    always @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0if (!rst) ch_1_t0_done<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0else if (en_1 && target_1==0 && cnt_t0_1==ch_1_size)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 ch_1_t0_done<=1;<\/span><\/p>\n

    always @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0if (!rst) ch_2_t0_done<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0else if (en_2 && target_2==0 && cnt_t0_2==ch_2_size)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 ch_2_t0_done<=1;<\/span><\/p>\n

    always @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (!rst) ch_3_t0_done<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else if (en_3 && target_3==0 && cnt_t0_3==ch_3_size)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 ch_3_t0_done<=1;<\/span><\/p>\n

    \/\/ \u4efb\u4e00\u901a\u9053\u5b8c\u6210\u5373\u603b\u5b8c\u6210<\/span>
    \nassign t0_done = ch_0_t0_done|ch_1_t0_done|ch_2_t0_done|ch_3_t0_done;<\/span><\/p>\n

    \/\/ \u65b9\u54110\u8bfb\u5199\u63a7\u5236<\/span>
    \nalways @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (!rst) t0_wr<=0; else t0_wr <= (s0_cs==S0_W_P);<\/span><\/p>\n

    always @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (!rst) t0_rd<=0; else t0_rd <= (s0_cs==S0_R_M);<\/span><\/p>\n

    \/\/ \u6e90\u5730\u5740\u81ea\u589e\uff1a\u6bcf\u53d6\u4e00\u4e2a\u5feb\u9012\uff0c\u5730\u5740+4<\/span>
    \nalways @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (!rst) rd_addr_0<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else if (en_0 && cnt_t0_0==0) rd_addr_0<=ch_0_sour;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else if (en_0 && s0_cs==S0_R_M) rd_addr_0<=rd_addr_0+4;<\/span><\/p>\n

    always @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (!rst) rd_addr_1<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else if (en_1 && cnt_t0_1==0) rd_addr_1<=ch_1_sour;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else if (en_1 && s0_cs==S0_R_M) rd_addr_1<=rd_addr_1+4;<\/span><\/p>\n

    \/\/ \u901a\u90532\u30013\u5730\u5740\u81ea\u589e\uff08\u903b\u8f91\u540c\u4e0a\uff09<\/span><\/p>\n

    \/\/ \u9009\u62e9\u5f53\u524d\u4f7f\u7528\u7684\u6e90\/\u76ee\u6807\u5730\u5740<\/span>
    \nassign t0_rm_addr = en_0 ? rd_addr_0 :<\/span>
    \nen_1 ? rd_addr_1 :<\/span>
    \nen_2 ? rd_addr_2 :<\/span>
    \nen_3 ? rd_addr_3 : 0;<\/span><\/p>\n

    assign t0_wp_addr = en_0 ? ch_0_dest :<\/span>
    \nen_1 ? ch_1_dest :<\/span>
    \nen_2 ? ch_2_dest :<\/span>
    \nen_3 ? ch_3_dest : 0;<\/span><\/p>\n

    \/\/ ==============================<\/span><\/strong>
    \n\/\/ \u65b9\u54111\u72b6\u6001\u673a\uff1a\u5916\u8bbe \u2192 \u5185\u5b58\uff08\u529e\u516c\u5ba4\u2192\u9001\u56de\u5feb\u9012\u70b9\uff09<\/span><\/strong>
    \n\/\/ ==============================<\/span><\/strong>
    \nreg [5:0] s1_cs;<\/span>
    \nreg [5:0] s1_ns;<\/span><\/p>\n

    parameter S1_IDLE = 6’b000000;<\/span>
    \nparameter S1_R_P = 6’b000001; \/\/ \u8bfb\u5916\u8bbe<\/span>
    \nparameter S1_WAIT_R = 6’b000010; \/\/ \u7b49\u5f85\u8bfb\u5230<\/span>
    \nparameter S1_W_M = 6’b000100; \/\/ \u5199\u5185\u5b58<\/span>
    \nparameter S1_WAIT_W = 6’b001000; \/\/ \u7b49\u5f85\u5199\u5b8c<\/span><\/p>\n

    \/\/ \u65b9\u54111\u4f7f\u80fd<\/span>
    \nassign ch0_t1_en=en_0 && target_0==1;<\/span>
    \nassign ch1_t1_en=en_1 && target_1==1;<\/span>
    \nassign ch2_t1_en=en_2 && target_2==1;<\/span>
    \nassign ch3_t1_en=en_3 && target_3==1;<\/span><\/p>\n

    \/\/ \u5916\u8bbe\u8bf7\u6c42\uff1aFIFO\u4e0d\u6ee1\uff0c\u53ef\u4ee5\u6536<\/span>
    \nassign peri_t1_req =(req_0&&ch0_t1_en&&fifo_0_full==0)||<\/span>
    \n(req_1&&ch1_t1_en&&fifo_1_full==0)||<\/span>
    \n(req_2&&ch2_t1_en&&fifo_2_full==0)||<\/span>
    \n(req_3&&ch3_t1_en&&fifo_3_full==0);<\/span><\/p>\n

    assign mem_t1_req = ch0_t1_en|ch1_t1_en|ch2_t1_en|ch3_t1_en;<\/span><\/p>\n

    \/\/ \u72b6\u6001\u673a\u65f6\u5e8f<\/span>
    \nalways @(posedge clk or negedge rst)<\/span>
    \nif (!rst) s1_cs<=S1_IDLE; else s1_cs<=s1_ns;<\/span><\/p>\n

    \/\/ \u72b6\u6001\u673a\u7ec4\u5408\u903b\u8f91<\/span>
    \nalways @(*)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0case (s1_cs)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0S1_IDLE: begin<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0if (peri_t1_req) s1_ns=S1_R_P;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0else if (mem_t1_req) s1_ns=S1_W_M;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0else s1_ns=S1_IDLE;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0end<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0S1_R_P: s1_ns=S1_WAIT_R;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0S1_WAIT_R: s1_ns=rd_en ? S1_IDLE : S1_WAIT_R;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0S1_W_M: s1_ns=S1_WAIT_W;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0S1_WAIT_W: s1_ns=hready_in ? S1_IDLE : S1_WAIT_W;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0default : s1_ns=S1_IDLE;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 endcase<\/span><\/p>\n

    \/\/ \u65b9\u54111\u8bfb\u5199\u63a7\u5236<\/span>
    \nalways @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (!rst) t1_wr<=0; else t1_wr <= (s1_cs==S1_W_M);<\/span><\/p>\n

    always @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (!rst) t1_rd<=0; else t1_rd <= (s1_cs==S1_R_P);<\/span><\/p>\n

    \/\/ \u4f7f\u80fd\u4fe1\u53f7\u8fb9\u6cbf\u68c0\u6d4b<\/span>
    \nalways @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (!rst) begin en_0_d<=0;en_1_d<=0;en_2_d<=0;en_3_d<=0; end<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else begin en_0_d<=en_0;en_1_d<=en_1;en_2_d<=en_2;en_3_d<=en_3; end<\/span><\/p>\n

    assign en_0_r = en_0 & ~en_0_d;<\/span>
    \nassign en_1_r = en_1 & ~en_1_d;<\/span>
    \nassign en_2_r = en_2 & ~en_2_d;<\/span>
    \nassign en_3_r = en_3 & ~en_3_d;<\/span><\/p>\n

    \/\/ \u65b9\u54111\u5730\u5740\u81ea\u589e<\/span>
    \nalways @(posedge clk or negedge rst)<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 if (!rst) rd_addr_t1_0<=0;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else if (en_0_r && ~en_0_r_d && target_0==1) rd_addr_t1_0<=ch_0_dest;<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 else if (en_0 && s1_cs==S1_WAIT_W) rd_addr_t1_0<=rd_addr_t1_0+4;<\/span><\/p>\n

    \/\/ \u901a\u90531\/2\/3\u65b9\u54111\u5730\u5740\u81ea\u589e\uff08\u903b\u8f91\u540c\u4e0a\uff09<\/span><\/p>\n

    \/\/ \u65b9\u54111\u5730\u5740\u9009\u62e9<\/span>
    \nassign t1_rp_addr = en_0?ch_0_sour:en_1?ch_1_sour:en_2?ch_2_sour:en_3?ch_3_sour:0;<\/span>
    \nassign t1_wm_addr = en_0?rd_addr_t1_0:en_1?rd_addr_t1_1:en_2?rd_addr_t1_2:en_3?rd_addr_t1_3:0;<\/span><\/p>\n

    \/\/ ==============================<\/span><\/strong>
    \n\/\/ FIFO \u63a7\u5236\u903b\u8f91<\/span><\/strong>
    \n\/\/ ==============================<\/span><\/strong>
    \nassign wr_fifo = rd_en; \/\/ \u53d6\u5230\u5feb\u9012\u5c31\u5199\u5165FIFO<\/span>
    \nassign wr_fifo_data = rdata; \/\/ \u5feb\u9012\u5185\u5bb9<\/span>
    \nassign rd_fifo_t0 = s0_cs==S0_W_P; \/\/ \u65b9\u54110\u8bfbFIFO<\/span>
    \nassign rd_fifo_t1 = s1_cs==S1_W_M; \/\/ \u65b9\u54111\u8bfbFIFO<\/span>
    \nassign rd_fifo = rd_fifo_t0 | rd_fifo_t1;<\/span><\/p>\n

    \/\/ \u5206\u901a\u9053\u63a7\u5236FIFO<\/span>
    \nassign wr_fifo_0 = en_0 && wr_fifo;<\/span>
    \nassign rd_fifo_0 = en_0 && rd_fifo;<\/span>
    \nassign wr_fifo_data_0 = en_0 ? wr_fifo_data : 0;<\/span><\/p>\n

    assign wr_fifo_1 = en_1 && wr_fifo;<\/span>
    \nassign rd_fifo_1 = en_1 && rd_fifo;<\/span>
    \nassign wr_fifo_data_1 = en_1 ? wr_fifo_data : 0;<\/span><\/p>\n

    assign wr_fifo_2 = en_2 && wr_fifo;<\/span>
    \nassign rd_fifo_2 = en_2 && rd_fifo;<\/span>
    \nassign wr_fifo_data_2 = en_2 ? wr_fifo_data : 0;<\/span><\/p>\n

    assign wr_fifo_3 = en_3 && wr_fifo;<\/span>
    \nassign rd_fifo_3 = en_3 && rd_fifo;<\/span>
    \nassign wr_fifo_data_3 = en_3 ? wr_fifo_data : 0;<\/span><\/p>\n

    \/\/ \u6700\u7ec8\u8f93\u51fa\u5730\u5740\u9009\u62e9<\/span>
    \nassign addr = t0_rd ? t0_rm_addr :<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 t0_wr ? t0_wp_addr :<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 t1_rd ? t1_rp_addr :<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 t1_wr ? t1_wm_addr : 0;<\/span><\/p>\n

    \/\/ \u8f93\u51fa\u6570\u636e\u9009\u62e9\uff08\u4eceFIFO\u53d6\uff09<\/span>
    \nassign wdata = wr ? (<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0en_0 ? rd_fifo_data_0 :<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0en_1 ? rd_fifo_data_1 :<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0en_2 ? rd_fifo_data_2 :<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0en_3 ? rd_fifo_data_3 : 0 ) : 0;<\/span><\/p>\n

    \/\/ \u6700\u7ec8\u8bfb\u5199\u547d\u4ee4<\/span>
    \nassign wr = t0_wr | t1_wr;<\/span>
    \nassign rd = t0_rd | t1_rd;<\/span><\/p>\n

    \/\/ \u4f20\u8f93\u5b8c\u6210\u4fe1\u53f7<\/span>
    \nassign req_done = (rd_en&&t0_mt_done)||(rd_en&&t0_done)||<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 (s0_cs==S0_WAIT_W&&hready_in)||<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 (s1_cs==S1_WAIT_R&&rd_en)||<\/span>
    \n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 (s1_cs==S1_WAIT_W&&hready_in);<\/span><\/p>\n

    endmodule<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"

    dmac_channel_ctrl = DMA \u52a9\u7406\u7684 \u201c\u603b\u8c03\u5ea6\u5458\u201d \u7ba1 4 \u4e2a\u901a\u9053\u30014 \u4e2a\u8d27\u67b6 \u7ba1\u6e90\u5730\u5740\u3001\u76ee\u6807\u5730\u5740\u3001\u642c\u8fd0\u957f\u5ea6 \u7ba1\u4ec0\u4e48\u65f6\u5019\u8bfb\u3001\u4ec0\u4e48\u65f6\u5019\u5199 \u7ba1 FIFO \u4ec0\u4e48\u65f6\u5019\u653e\u8d27\u3001\u4ec0\u4e48\u65f6\u5019\u53d6\u8d27 \u6307\u6325 AHB \u63a7\u5236\u5668\u53bb\u4e3b\u5e72\u9053\u8fd0\u8f93 dmac_channel_ctrl \u662f DMA \u7684 4 \u901a\u9053\u603b\u8c03\u5ea6\u5458\u3002\u8001\u5e08\uff08CPU\uff09\u4e0b\u8fbe\u4efb\u52a1\u540e\uff0c\u8c03\u5ea6\u5458\u6839\u636e\u6e90\u5730\u5740\u3001\u76ee\u6807\u5730\u5740\u3001\u642c\u8fd0\u957f\u5ea6\uff0c\u63a7\u5236\u4e24\u4e2a\u72b6\u6001\u673a\u5206\u522b\u5904\u7406 \u201c\u5185\u5b58\u2192\u5916\u8bbe\u201d \u548c \u201c\u5916\u8bbe\u2192\u5185\u5b58\u201d \u4e24\u79cd\u642c\u8fd0\u65b9\u5411\uff0c\u81ea\u52a8\u5730\u5740\u81ea\u589e\u3001\u8ba1\u6570\u3001\u5224\u65ad FIFO \u7a7a\u6ee1\uff0c\u6307\u6325 AHB \u63a7\u5236\u5668\u5b8c\u6210\u8fd0\u8f93\uff0c\u5e76\u628a\u5feb\u9012\u6682\u5b58\u5230\u5bf9\u5e94\u8d27\u67b6\uff0c\u4efb\u52a1\u5b8c\u6210\u540e\u901a\u77e5\u7cfb\u7edf\u3002\u6574\u4e2a\u8fc7\u7a0b\u5168\u81ea\u52a8\uff0c\u4e0d\u7528\u8001\u5e08\u63d2\u624b\u3002 `timescale 1ns\/10ps \/\/ ============================== \/\/ \u6a21\u5757\uff1admac_channel_ctrl \/\/ \u529f\u80fd\uff1aDMA 4\u901a\u9053\u603b\u63a7\u5236\u5668\uff08\u603b\u8c03\u5ea6\u5458\uff09 \/\/ \u573a\u666f\uff1a\u3010\u52a9\u7406\u624b\u4e0b\u7684\u5feb\u9012\u603b\u8c03\u5ea6\u3011 \/\/ \u4f5c\u7528\uff1a\u7edf\u4e00\u7ba1\u74064\u8def\u65e0\u4eba\u673a\u8fd0\u8f93\uff0c\u63a7\u5236\u5730\u5740\u3001\u8ba1\u6570\u3001FIFO\u3001\u72b6\u6001\u673a \/\/ ============================== module dmac_channel_ctrl( \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 input clk, \/\/ \u5de5\u4f5c\u8282\u62cd \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 input rst, \/\/ \u7cfb\u7edf\u590d\u4f4d\uff0c\u5168\u90e8\u91cd\u6765 \/\/ 4\u4e2a\u901a\u9053\u7684\u8bf7\u6c42\u4fe1\u53f7\uff1a\u8c01\u8981\u5e72\u6d3b input req_0, req_1, req_2, req_3, \/\/ \u5bf9\u63a5AHB\u63a7\u5236\u5668\uff08\u9053\u8def\u7ba1\u7406\u5458\uff09 output wr, \/\/ \u5199\u547d\u4ee4\uff1a\u9001\u5feb\u9012 output rd, \/\/ \u8bfb\u547d\u4ee4\uff1a\u53d6\u5feb\u9012 output [31:0] addr, \/\/ \u5730\u5740\uff1a\u53bb\u54ea\u53d6\/\u9001\u5230\u54ea output [31:0] wdata, \/\/ \u8981\u9001\u7684\u5feb\u9012 input [31:0] rdata, \/\/ \u53d6\u56de\u6765\u7684\u5feb\u9012 input rd_en, \/\/ \u53d6\u5230\u6709\u6548\u5feb\u9012 \/\/ \u901a\u9053\u4f7f\u80fd\uff1a\u54ea\u4e2a\u901a\u9053\u542f\u52a8 input en_0,en_1,en_2,en_3, \/\/ \u4f20\u8f93\u65b9\u5411\uff1a0=\u5185\u5b58\u2192\u5916\u8bbe 1=\u5916\u8bbe\u2192\u5185\u5b58 input target_0,target_1,target_2,target_3, \/\/ \u6bcf\u4e2a\u901a\u9053\u8981\u642c\u591a\u5c11\u5feb\u9012 input [9:0] ch_0_size,ch_1_size,ch_2_size,ch_3_size, \/\/ \u6e90\u5730\u5740\u3001\u76ee\u6807\u5730\u5740 input [31:0] ch_0_sour,ch_0_dest, input [31:0] ch_1_sour,ch_1_dest, input [31:0] ch_2_sour,ch_2_dest, input [31:0] ch_3_sour,ch_3_dest, \/\/ FIFO\u7a7a\/\u6ee1\u72b6\u6001 input fifo_0_empty,fifo_1_empty,fifo_2_empty,fifo_3_empty, input fifo_0_full,fifo_1_full,fifo_2_full,fifo_3_full, \/\/ \u63a7\u5236FIFO\uff1a\u653e\u5feb\u9012\u3001\u53d6\u5feb\u9012 output wr_fifo_0, wr_fifo_data_0, rd_fifo_0, input [31:0] rd_fifo_data_0, output wr_fifo_1, wr_fifo_data_1, rd_fifo_1, input [31:0] rd_fifo_data_1, output wr_fifo_2, wr_fifo_data_2, rd_fifo_2, input [31:0] rd_fifo_data_2, output wr_fifo_3, wr_fifo_data_3, rd_fifo_3, input [31:0] rd_fifo_data_3, input hready_in, \/\/ \u5bf9\u65b9\u5df2\u5c31\u7eea output req_done, \/\/ \u672c\u6b21\u4f20\u8f93\u5b8c\u6210 \/\/ 4\u4e2a\u901a\u9053\u4efb\u52a1\u5b8c\u6210\u6807\u5fd7 output reg ch_0_t0_done, output reg ch_1_t0_done, output reg ch_2_t0_done, output reg ch_3_t0_done ); parameter MAX_TRANS=8; \/\/ \u4e00\u6b21\u6700\u591a\u642c8\u4e2a parameter TRANS_W=3; \/\/ \u6bcf\u4e2a\u901a\u9053\u5df2\u642c\u8fd0\u8ba1\u6570 reg [9:0] cnt_t0_0,cnt_t0_1,cnt_t0_2,cnt_t0_3; reg [TRANS_W-1:0] t0_cnt; \/\/ \u7a81\u53d1\u4f20\u8f93\u8ba1\u6570\u5668 wire t0_mt_done; \/\/ \u4e00\u6b21\u7a81\u53d1\u5b8c\u6210 \/\/ \u65b9\u54110\uff1a\u5185\u5b58 \u2192 \u5916\u8bbe\uff08\u53d6\u5feb\u9012\u2192\u9001\u529e\u516c\u5ba4\uff09 wire peri_t0_req; wire mem_t0_req; \/\/ \u65b9\u54111\uff1a\u5916\u8bbe \u2192 \u5185\u5b58\uff08\u529e\u516c\u5ba4\u2192\u9001\u56de\u5feb\u9012…<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-1402","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"_links":{"self":[{"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/posts\/1402","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/comments?post=1402"}],"version-history":[{"count":4,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/posts\/1402\/revisions"}],"predecessor-version":[{"id":1407,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/posts\/1402\/revisions\/1407"}],"wp:attachment":[{"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/media?parent=1402"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/categories?post=1402"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.hanhhsir.cn\/index.php\/wp-json\/wp\/v2\/tags?post=1402"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}